FIG. 1 shows a typical data path structure having a Bit Line Sense Amplifier (BLSA) PSA,NSA,LA,LAB, Data Input/Output lines (DIO,DIOB), Column Select Line (CSL), Memory Cell (MC): a capacitor C and an access transistor N5, Bit Line (BL), Complementary Bit Line (BLB), Data output sense amplifier 10, Loads (L1,L2), and Word Line (WL). The term DIOB refers to a complementary data IO line. A typical BLSA includes a PMOS sense amplifier (PSA) and an NMOS sense amplifier (NSA) connected to the BL and the BLB respectively.
A read operation is performed as follows. Before WL activation, the BL and the BLB are pre-charged at the same voltage level by a VBL voltage generator and an equalizing and pre-charging circuit (not shown). The VBL level is half the voltage level of VCC. If a row active command in combination with a row address is applied to a DRAM, a WL relevant to the row address is activated. The charge in a capacitor C couples and shares with the charge of the BL. This is referred to as a xe2x80x9cCharge Sharing (CS)xe2x80x9d operation.
A slight voltage difference between BL and BLB is generated by the CS operation, and then sense-amplified by the PSA and NSA circuits in conjunction with the sense amplifier enabling signals LA and LAB. If the charge in the capacitor C is logically xe2x80x9chighxe2x80x9d in other words xe2x80x9cVCCxe2x80x9d, the BL is logically xe2x80x9chighxe2x80x9d and the BLB is logically xe2x80x9clowxe2x80x9d during the CS operation and sense-amplifying operation. The amplified data in the BL/BLB are transferred to the DIO/DIOB lines in response to a CSL signal through transistors N3 and N4, respectively. The CSL signal is enabled by a read command or write command in combination with a column address.
Two load transistors L1 and L2 are used by the data output sense amplifier 10. The load transistors L1 and L2 comprise a PMOS or NMOS transistor connected to a certain power voltage like a supply power or ground power to provide a current to the DIO and DIOB lines during a read operation. The data transferred to the DIO and DIOB lines is amplified by the data output sense amplifier 10. The amplified data is output externally through a data output buffer 20 in response to a signal (not shown).
The time between a row active command and the output of data is called the access time (tRAC). The process technology of the prior art provides a charge sharing (CS) time of about 10 ns and an access time of about 40 nanoseconds (ns) or so. In the BLSA structure shown in FIG. 1, the CS time and sense-amplifying time (SEN time) must take place before the CSL enables the charge from the BL and BLB lines onto the DIO and DIOB lines.
The capacitive loading of the DIO/DIOB lines is larger than that of the BL/BLB lines by about 10 times. If the CSL enables before BL sensing at a certain voltage level, say a delta VBL of between 0.5 Volts (V) and 1V or so, the data on the BL and BLB lines cannot be sense amplified. The voltage difference between the BL and BLB is called delta VBL. This BLSA structure is available for Dynamic Random Access Memories (DRAMs) that do not care about the CS and SEN times.
The access time tRAC can be reduced by reducing the CS time and SEN time. DRAMs with access times tRAC of about 20 ns are referred to as high-speed DRAMs or Fast Cycle Random Access Memory (FCRAM). Data input buffer 30 are used for the write operation. DIN is the data input. The data output sense amplifier 10 is used for read operations.
FIG. 2 shows a timing diagram for FIG. 1 when the read operation data is xe2x80x9c1xe2x80x9d. Every command is synchronized with the rising edge of the clock signal. A ROW ACTIVE command with address (row address) enables a specific Word Line (WL). A READ command with address (column address) enables the CSL signal. In the structure of FIG. 1, the CS time and SEN time should be completed before the CSL line is enabled. The enable point for the LA and LAB is determined by the memory chip designer. After the CSL is enabled, the data on the BL and BLB lines is transferred to the DIO and DIOB lines. Finally, the data on the DIO and DIOB lines is transferred to the data output buffer (DOUT) 20. The DOUT is normally pre-charged at a Hi-Z level before the data is transferred.
FIG. 3 shows a typical data path structure for a conventional high-speed Bit line Sense Amplifier (BLSA) in a semiconductor memory device. This BLSA is described in farther detail in xe2x80x9cA 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecturexe2x80x9d Taguchi et. al. IEEE Journal of solid state circuit, Vol.26, NO.11, pp.1493xcx9c1497, November 1991xe2x80x9d.
FIG. 3 shows separate Column Select Lines (CSLs) WCSL and RCSL and separate data lines RDO/RDOB and WDI/WDIB for read and write operations, respectively. For the high-speed read operation, a direct sense amplifier is implemented in the BLSA and is referred to as a Read Sense Amplifier (RSA). The RSA operates like a differential amplifier. In this disclosure, Direct SA, RSA and differential amplifier mean the same thing. A slight voltage difference is amplified by the RSA. In this case, the RCSL enable timing can be faster than the CSL timing shown in the FIG. 1 scheme. A designer can select the CSL enable timing point, then design a shorter tRAC for the FCRAM.
Since RCSL may be activated even before the WL is activated, most of the CS time and SEN time is not required in this scheme. In other words, as soon as WL is activated, RCSL can be activated. If a slight voltage difference exists between the BL and the BLB, RSA amplifies the BL and the BLB without the PSA and NSA. Data errors seldom occur in this scheme. Although the loading of the DIO line is large, this differential amplifier RSA can amplify the slight difference of the voltage.
However, this scheme has a problem. By implementing the RSA, the read and write paths need to be implemented separately so that data contention does not occur during the read operation and write operations. This requires a larger IC layout area than any other sense amplifier schemes.
FIG. 4 shows a timing diagram for FIG. 3 when data is xe2x80x9c1xe2x80x9d. As shown, RCSL reduces the enabling time. Most of the CS time and SEN time is not needed to enable the CSL. This provides faster RCSL enabling and as a result a shorter access time tRAC.
FIG. 5 shows another typical data path structure that includes a conventional high-speed BLSA for a semiconductor memory device. The WR signal is only used when a write command is entered. The WR signal does not include any address information. The CSL is used during both write and read operations. Data input lines and output lines are also commonly used. The DIOG3 includes 4 transistors, N11, N12, N13 and N14. The DIOG3 Data Input/Output gate transistors considerably increase the layout area in DRAMs. Another problem is an increase in the current consumption caused by the RSA operating for both read and write operations in response to the WR and CSL.
The present invention addresses this and other problems associated with the prior art.
A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit.
A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.